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CDB42L55
3 CONFIGURATION OPTIONS
This section highlights two common configurations for the CDB42L55. It provides a basic understanding of how the
various components on the board work together.
3.1
S/PDIF or PSIA In to Analog Out
The CS42L55 analog back-end performance can be tested by selecting the “SPDIF In to Analog Out --
Analog In to S/PDIF Out” or “PSIA In to Analog Out -- Analog In to PSIA Out” quick setup file provided
with the software package. Note: The Control Port Compensation script for the associated VA supply
must also be selected. The script configures the digital clock and data signal routing on the board as shown
in Figure 2 . The quick setup scripts provided in the software assume that a 24.000 MHz on-board oscillator
is populated in Y1.
A S/PDIF input must be provided as the S/PDIF Tx (CS8406) uses the RMCK signal from the S/PDIF Rx
(CS8416) for synchronization in this configuration.
An on-board PLL generates all supported sample and
bit clock rates from an on-board 24 MHz oscillator.
FPGA
PLL
MCLK
24 MHz
(on-board osc.)
PSIA Tx (J78)
Tx SRC
(CS8421)
CS42L55
TX.SCLK Out
TX.LRCK Out
SCLK
LINEOUTB
B
TX.SDOUT
LRCK
LINEOUTA
A
Line
Channel
S/PDIF Rx
(CS8416)
RX.LRCK
HPOUTB
DAC.SDIN
J4
32
32
16
16
J3
B
RX.SCLK
HPOUTA
J12
J2
HP
A
Channel
S/PDIF
RX.SDOUT
IN
(Master)
(Slave)
(Slave)
J21
HP
Connection
Figure 2. S/PDIF or PSIA In to Analog Out
8
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